1. Field of the Invention
The present invention relates generally to circuitized substrates and more specifically to a process for removal of undesirable conductive material (e.g., a catalyst layer) on a printed circuit and the resultant printed circuit.
2. Description of the Related Art
In the manufacture of printed circuit boards, a conductive circuit pattern is provided on at least one surface of a dielectric substrate. The circuit pattern can be formed on the substrate using a variety of known techniques. One of the better known techniques includes the electroless direct bond (EDB) technique, wherein copper is electrolessly plated directly onto the surface of the substrate in a desired pattern. The circuit pattern may include conductor lines on the surface of the substrate as well as in holes (often referred to as plated through holes) which connect one or more of the conductive layers together. Since the dielectric substrate is non-conductive, it is generally necessary to catalyze the substrate prior to deposition of the conductive metal onto the substrate. Among the more widely employed procedures for catalyzing is to deposit colloidal particles of palladium (Pd) and tin (Sn) onto the substrate. A resist layer is then applied over the catalyst layer. A circuit pattern is formed by first removal of portions of the resist through masking techniques. Then, a copper metallic coating can then be applied to the exposed catalyzed areas or areas where the resist has been removed by way of known processing such as electroless deposition techniques to form the circuit pattern. Following the electroless deposition of the metallic coating, the remaining resist is removed.
One of the difficulties not adequately addressed heretofore occurs after the remaining resist has been removed, a residual catalyst layer (e.g., tin and palladium layer) remains between the circuit features (e.g. lines) of the circuit pattern. The term "residual" as used hereinafter, refers to undesirable material between circuit features of the circuit pattern. Another difficulty is that when the catalyst layer has a circuit pattern deposited thereon, trace amounts of the circuit material (e.g., copper) in the circuit pattern, seep under the resist into the residual catalyst layer which causes further electrical shorting. If the catalyst layer and residual circuit material are not adequately removed, electrical shorting between the circuit features of the finished circuit pattern occurs due to the residual catalyst material and residual seeped circuit material (e.g., copper).
U.S. Pat. No. 4,718,972 assigned to International Business Machines Corporation discloses one proposed method of making a PCB wherein metallic seed (catalyst) particles are applied to a surface of a substrate. An image of the desired conductor pattern is defined by a maskant layer to permit the subsequent electroless deposition of the conductor material upon the exposed seeded areas of the substrate. Then, the substrate surface is subjected to a plasma discharge to facilitate removal of the seed particles. This method, however, has not provided complete removal of the catalyst and seeped circuit material between the circuit features.
Heretofore, the related art does not disclose complete removal of the residual catalyst material and residual seeped circuit material. If the residual catalyst layer and circuit material are not completely removed, they result in yield losses because of the shorts created. Such a decrease in product yield becomes quite costly when processing large amounts of circuitized substrates.